High Performance Ethernet Packet Processor Core for Next Generation Networks
نویسندگان
چکیده
منابع مشابه
High Performance Ethernet Packet Processor Core for next Generation Networks
As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high performance, low power and high degree of programmability is the limitation in many general pr...
متن کاملEthernet Packet Processor for SoC Application
As the demand for Internet expands significantly in numbers of users, servers, IP addresses, switches and routers, the IP based network architecture must evolve and change. The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many processor based applications. This paper describes the design of ethernet packet ...
متن کاملEnabling next Generation Ethernet Access with Ethernet Passive Optical Networks
This article describes Ethernet Passive Optical Networks (EPONs), an emerging local subscriber access architecture that combines low cost point-to-multipoint fiber infrastructure with Ethernet. EPONs are designed to carry Ethernet frames at standard Ethernet rates. EPONs use a single trunk fiber that extends from a central office to a passive optical splitter, which then fans out to multiple op...
متن کاملNetwork Processor Architecture for Next Generation Packet Format
Over the past few years, network processors have become an important component in packet delivery over the internet with its packet processing rate determining the bottleneck of usage of bandwidth of transmission medium. The architectures of network processors have mainly focused on achieving a particular line rate for IPv4 packets. As the usage of new format IPv6 increases, changes in architec...
متن کاملProgrammable Gigabit Ethernet Packet Processor Design Methodology
The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many applications. In this paper, a novel design methodology to support the development of such a processor is described. This design methodology will be illustrated with the design of a forwarding engine of a Gigabit Ethernet router. Indeed, this forwarding ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Next-Generation Networks
سال: 2012
ISSN: 0975-7252
DOI: 10.5121/ijngn.2012.4307